Digital PLL frequency synthesizer

ABSTRACT

A digital frequency synthesizer includes a digital-to-analog (1), a low pass filter (2), and a controllable oscillator (3), where the oscillator output is the synthesizer output. K number of RS flip-flops (101-108) produce error signals which are coupled to the DAC. The S inputs of the flip-flops come from a phase-splitter (8) which is driven by the more-significant bits unit of an accumulator (5) which is clocked by a reference frequency. The R inputs of the same flip-flops get input pulses from a pulse distributor (9) which is driven by the synthesizer output. The frequency resolution can be increased by adding a less-significant bits accumulator (15), coupled to the more-significant bits unit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to frequency synthesizers and, in particular, todigital frequency synthesizers using a phase locked loop (PLL) toproduce a signal having a frequency f_(s) which is a rational fractionof a reference frequency f_(r) according to the relationship:

    f.sub.s =(a/b)·f.sub.r                            ( 1)

where a and b are positive integers. Synthesizers of this kind areuseful in variety of applications including, but not limited to,telecommunications systems and radio measurement equipment.

2. State of the Art

A known digital frequency synthesizer is disclosed in U.S. Pat. No.3,913,028 to Bosselaers. This known synthesizer uses an oscillator, aspart of a PLL, controlled by a signal from an arithmetic unit, combinedwith a digital-to-analog converter (DAC), and a low-pass filter. Thisarchitecture permits a high speed of operation and high resolution infrequency, but lacks the spectral purity of output signal required inmany cases. Modern telecommunications and radio measurement equipmentrequire frequency synthesizers which have a high spectral purity ofoutput in addition to a high speed of operation and high resolution infrequency.

A series of advanced frequency synthesizers providing a signal of betterspectral purity are disclosed in Kozlov, V. I., Frequency SynthesizersBased on Using Accumulators, Electrosvyaz, 1988, No.2, pp. 53-56 (theEnglish translation of this magazine is published in the U.S.A. byScripta Publishing Company, under the title, "Telecommunications andRadio Engineering"). These synthesizers are based on a digital phasedemodulation of two pulse trains, reference and controllable, havingdifferent frequencies, and utilize accumulators, an RS flip-flop and aDAC. The result of phase comparison of these two pulse trains is fedfrom the DAC, via a low-pass filter, to a controllable oscillator whoseoutput is adjusted by the PLL to whatever relationship with thereference frequency is required. The desired signal frequency isdetermined by code-setting of the inputs to the accumulators. Theimprovement in signal spectral purity, gained in this way, is notenough, however. The signal spectrum still contains some discretecomponents, which may be called fractional spurs, because thefrequencies of the reference signal and output pulse trains are not ininteger relationship with each other. The level of these fractionalspurs depends on the accuracy of the DAC which, in turn, is limited bythe current technological state of the art. For example, using an 8-bitDAC, the level of fractional spurs is typically no less than -48 dBc. Inmany cases, this level of fractional spurs is unacceptable. The problemof minimizing these spurs is still a prime concern in the design offrequency synthesizers.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide a frequencysynthesizer utilizing a DAC where the spectral purity of the outputsignal is improved over the current art for a DAC of given accuracy.

It is also an object of the invention to provide a frequency synthesizerwhich has a high speed of operation and a high resolution in frequency.

In accord with these objects which will be discussed in detail below,the synthesizer of the present invention includes a DAC with its analogoutput coupled to a low-pass filter which, in turn, is coupled to acontrolled oscillator (VCO) whose output is the output of thesynthesizer. A frequency to be synthesized is selected by a binarynumber which is input to a first accumulator. The outputs of the firstaccumulator are fed through a phase splitter having K outputs (whereK=2^(k) and k is the number of the accumulator's bits) which are eachcoupled to the S input of a respective RS flip-flop. The output of eachof the flip-flops is coupled to first equally weighted inputs of theDAC. A reference frequency serves as the clock input for the accumulatorand the phase splitter. The output signal of the VCO is coupled to theclock input of a pulse distributor having w outputs each of which iscoupled to the R input of a respective number (K/w) of the RS flip-flops(where K/w is an integer).

According to the invention, all of the DAC bits supplied by the RSflip-flops have equal weight. Therefore, to get the same level of thefractional spurs, the amplitude accuracy required of them, may be Ktimes lower than in the known synthesizers. That means that given thesame accuracy of DAC, the level of the fractional spurs will be K timeslower. The time matching required of the DAC bits can be less severesince, in this case, time mismatching increases only higher-frequencyfractional interferences which may be filtered out by the PLL. The DACcan be based on a KR-type resistive ladder.

In one embodiment, the pulse distributor is a ring counter, whichgreatly simplifies the synthesizer. In this embodiment, output signalfrequency f_(s) is determined according to the equation

    f.sub.s =w·x·f.sub.r /q,                 (2)

where w is the ring counter capacity, x is the input number toaccumulator, q is the capacity of accumulator, and f_(r) is thereference (clock) frequency.

If there is a need to use a relatively small value of w, several timesless than q, then all RS flip-flops should be subdivided into w numberof batches, with K/w flip-flops in each batch. In each batch, all Rinputs of the flip-flops are connected to a corresponding output of thering counter. This permits the value of w to be chosen from among a widerange of values.

The first accumulator can be supplemented with m number of lesssignificant bits. This decreases the step size due to the increased fullcapacity of the accumulator, thereby increasing frequency resolution Δfaccording to the equation:

    Δf=f.sub.r q                                         (3)

where the accumulator's full capacity q=2^(n), with n=k+m. This givesrise to an interference having a maximum period of 2^(m) times thereference period, where m is the number of less-significant bits added.If the value of m is relatively small, the minimum interfering frequencyis sufficiently high to be filtered out by PLL action. Otherwise, someway of suppressing this interference has to be found.

To suppress the interferences in this latter case, the output of thegroup of less-significant bits is connected to a second input of theDAC, whose less significant bits may be built using an R-2R typeresistive ladder. These less significant bits are added to the moresignificant bits with the aid of a matching resistor; e.g., since theirweight is 1/K of the full scale output signal of the DAC, the accuracydemanded of the most significant bit of them has the same low value asfor each of the more significant bits, and for the less significantbits, accuracy demanded is even lower, correspondingly.

For the above-described embodiments of the invention, the frequencyresolution can be made as high as desired by increasing full capacity ofthe accumulator. But, in these cases, the frequency step size and thereference frequency cannot be chosen independently, to make bothconvenient, e.g. for decimal steps, which is, in some cases, desirableor necessary. However, the choice of frequency step size can be enhancedby implementing the pulse distributor as a unit containing a secondaccumulator and a second phase splitter, the clock inputs of both beingconnected to the output of the synthesizer. Data input to the secondaccumulator is connected to a second data bus, which serves to code setthe frequency step size. Implementing the equation, f_(s) =(a/b)·f_(r),the signal frequency f_(s) is set by the code number a applied to theinput of the first accumulator, and the frequency step size Δf=f_(r) /bis code-set by number b at the input of the second accumulator. If asmaller step size is desired, a group of the less significant bits maybe added as explained above with reference to the first accumulator.That is, the LSB output of the second accumulator can be connected to athird input of the DAC, which in this case, can be implemented by usingan added R-4R/2 type resistive ladder.

Each of the two identical phase splitters contains a binary code tolinear code transcoder, the number of units in the linear code beingequal to the current value of the binary code at the output of itscorresponding accumulator. The phase splitter also contains K number ofchains, each chain containing a D flip-flop, a first AND gate, amultiplexer, and a second AND gate. Each of these chains is connected toa corresponding output of the transcoder. All of the D flip-flop clockinputs, and one of the inputs of the second AND gate are connected to acommon clock input of the phase splitter. The controlling input to themultiplexer is connected to an output of overflow pulses, which isincorporated in the output bus of the corresponding accumulator; and oneof the inputs of the first AND gate is connected to the data input ofthe D flip-flop, which input also serves as the input to the chain. Ineach of the K/2 chains, corresponding to less significant bits, anotherinput to the multiplexer is connected to the input of the chain, and, inthe K/2 chains remaining, a multiplexer input is connected to the outputof the D flip-flop.

In order to further reduce demands on DAC accuracy, each of the lesssignificant bits portions of the first and second accumulators areprovided with an averaging unit which is clocked by reference or outputsignal pulses accordingly. Each of these averaging units may include anaveraging accumulator having a capacity which is p bits more than therespective first or second accumulator and a register which is clockedby pulses having a frequency 2P times lower with the aid of a frequencydivider. In this way, the frequency of switching in less significantbits of the DAC can be reduced to the frequency of switching in the moresignificant bits. This allows the use of a less accurate (slower acting)DAC or improves the spectral purity even further using a DAC ofcomparable accuracy.

This invention improves the spectral purity of a frequency synthesizeroutput signal without imposing severe demands on DAC accuracy. Forexample, known frequency synthesizers using DACs with an accuracy of an8-bit device typically provide a level of fractional spurs of no lessthan -48 dBc. In a synthesizer according to the invention, these spurscan be lowered to -90 dBc or less, using a DAC of the same accuracy.Additional objects and advantages of the invention will become apparentto those skilled in the art upon reference to the detailed descriptiontaken in conjunction with the provided figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a first embodiment of the frequencysynthesizer according to the invention;

FIGS. 2a through 2g are timing diagrams illustrating the basicprinciples of operation of the first embodiment of the invention;

FIG. 3 is a schematic diagram of a KR resistive ladder embodiment of theDAC according to a first embodiment of the invention;

FIG. 4 is a schematic diagram of an embodiment of the DAC having a KRresistive ladder coupled to an R-2R resistive ladder;

FIG. 5 is a schematic diagram of one embodiment of a phase splitter;

FIGS. 6a through 6e are timing diagrams illustrating the inputs andoutputs of the RS flip-flops according to a first embodiment of theinvention;

FIG. 7 is a block diagram showing the connection of a four output pulsedistributor to eight RS flip-flops;

FIGS. 8a-8e are timing diagrams illustrating the inputs and outputs ofthe RS flip-flops according to a second embodiment of the invention;

FIGS. 9a-9e are timing diagrams illustrating the inputs and outputs ofthe RS flip-flops according to a third embodiment of the invention;

FIG. 10 is a view similar to FIG. 1, but of a fourth embodiment of theinvention;

FIG. 11 is a schematic diagram of an embodiment of the DAC having a KRresistive ladder coupled to an R-4R/2 resistive ladder;

FIG. 12 is a schematic diagram of one embodiment of a less significantbits portion of the first and second accumulators; and

FIGS. 13a and 13b are timing diagrams illustrating the outputs of theless significant bits portions of FIG. 12.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A first embodiment of the invention is shown schematically in FIG. 1.According to this embodiment, an accumulator is shown by units 5 and 15,of more significant and less significant bits, respectively, connectedto each other by carry network 17. Data inputs of the units areconnected to a first data bus 6, which gets a number X, determining thesynthesizer frequency. A first phase splitter 8, which is described inmore detail below, has a data input 12 which receives a variable codenumber from the output of accumulator unit 5. Reference frequency pulsesf_(r) are supplied to a reference input 7 of the frequency synthesizer,and are coupled via a clock bus 13 to the clock inputs C of theaccumulator units 5, 15 and the first phase splitter 8. The outputs ofthe phase splitter 8 are each coupled to the S input of a respective RSflip-flop , e.g. 101 through 108, and the output of each flip-flop iscoupled to an equally weighted digital input 10 of a DAC 1. The analogoutput 11 of DAC 1 is coupled to a low pass filter 2 which in turnprovides input for a controllable oscillator 3. The output 4 of theoscillator 3 is the synthesizer output, but is also coupled via a clockbus 14 to the clock input C of a pulse distributor 9 which is describedin more detail below. The outputs of the pulse distributor 9 are coupledto respective R inputs of the RS flip-flops 101-108. The DAC 1, low passfilter 2, controllable oscillator 3, pulse distributor 9, and flip-flops101-108 together form a phase locked loop. The RS flip-flops and the DACtogether serve as a phase-sensitive demodulator, whose output signal isused to control the controllable oscillator 3.

Turning now to FIGS. 2a through 2g and with reference to FIG. 1, theprinciple of operation of the synthesizer of the invention isillustrated in a simplified case using four RS flip-flops. If the numberX on the first data bus 6 is not in integer relationship with thecapacity q of the accumulator, the pulse signal E(t), as shown in FIG.2a, which is the output of a single flip-flop in a known synthesizer, iscontaminated by fractional interferences, which modulate a duty cycle ofthe process signal E(t). The largest period of these interferencesequals q periods. See, for example, the averaged value E_(i) (t) of theprocess signal E(t). It will be appreciated that there are K number ofsignals like E(t), one for each flip-flop. FIGS. 2b through 2e show theindividual signals e(t) of four flip-flops which are shifted withrespect to each other by the phase splitter 8. Each of these signals isshifted by M number of periods where M=q/K, K being the capacity of themore significant bits unit 5 of the accumulator 5, 15. It will beappreciated that K=2^(k) where k is the number of more significant bitsand that M=2^(m) where m is the number of less significant bits in theless significant bits unit 15 of the accumulator which does notparticipate in the phase splitting.

As mentioned above, each of the signals e(t) is given equal weight andthus the sum of these signals produces a constant E_(y) =K·e, wheree=E_(y) /K is a constant component in each of the added signals e(t).The interference components e_(i) (t) of each signal each have astarting period of q clock periods so that they are summed in such a waythat an interference e_(i) ^(*) (t) having K times higher frequency, andK times lower amplitude results as shown in FIG. 2f. In actual practice,the constant components of the individual signals may differ from eachother because of the presence, in some of them, of some constantincrement to the duration of each pulse, due to a limited capacity ofthe pulse distributor 9. However, the fractional interferences make allthe averaged values of the processes change in the same way.

The period of the interference signal e_(i) ^(*) (t), which equals Mclock periods, and the wave form of the interference, are determined bythe less significant bits of the accumulator, which do not contribute tothe phase-splitting process. The sum of the outputs of the lesssignificant bits unit 15 of the accumulator 5, 15 is shown in FIG. 2g.It will be appreciated that this signal e_(c) (t) is out-of-phase withthe interference signal e_(i) ^(*) (t), and can be used to cancel outthe remnant fractional interference.

From the foregoing, it will be appreciated that the summing of the e(t)signals produced by the RS flip-flops can be accomplished with a KR-typeresistive ladder as shown in FIG. 3. Moreover, the sum of the lesssignificant bits signal to form the canceling signal e_(c) (t) can beaccomplished with an R-2R-type resistive ladder such as seen in FIG. 4.As shown in FIG. 4, these two ladders are combined with the aid ofmatching resistor R^(*). If the resistors in the KR-type ladder arechosen to be 2R, then the matching resistor should be R.

Returning now to FIG. 1, it will be appreciated that the phase splitter8 transmits f_(r) pulses to the S-inputs of flip-flops 101 through 108in a strictly defined sequence. As shown in FIG. 1, the number of bits kof the more significant bits accumulator unit 5 is k=3 so that K=8. If,for example, the code number X applied to the data bus 6 is such thatthe more significant bits portion X_(m) =3, then in one of the f_(r)clock periods pulses arrive simultaneously at the S inputs of flip-flops101 through 103. In the next clock period, pulses arrive simultaneouslyat the S inputs of flip-flops 104 trough 106; then, to flip-flops 107,108, and 101; then, to flip-flops 102 through 104 and so on, in acircle. The carry from the less significant bits unit 15 to the moresignificant bits unit 5, if it arises on some of the clock periods, isequivalent to a unity increment of the X_(m) number; hence, in this sameclock period, the pulses arrive at four, instead of three, consecutiveflip-flops.

The phase splitter 8 may be constructed in many ways, the presentlypreferred construction being illustrated in FIG. 5. In this embodiment,the phase splitter includes a binary to linear transcoder 80 and Knumber of chains, e.g. 201-208. The transcoder 80 receives data inputfrom the output bus 12 of the more significant bits accumulator 5,described above with reference to FIG. 1, and provides outputs to thechains as described below. The clock input C of the transcoder 80 iscoupled to the clock bus 13 described above. Each of the chains, 201through 208 in this example, is composed of a D-flip-flop 81, a firstAND gate 82, a multiplexer 83 and a second AND gate 84, all connected insequence. In each chain, the clock input C of the D flip-flop 81 and oneof the inputs of the second AND gate 84 are coupled to the clock bus 13.The controlling input of the multiplexer 83 is coupled to an output ofoverflow pulses 85 which is part of the output bus 12 of the accumulatorunit 5. In half of the chains, 201-204, representing the lesssignificant bits of the code number X_(m), the input of the chain iscoupled to the D input of the flip-flop 81, an input of the first ANDgate 82, and one of the inputs of the multiplexer 83. The output of theD flip-flop 81 is coupled to the other input of the first AND gate 82.The output of the first AND gate 82 is coupled to another input of themultiplexer 83, and the output of the multiplexer 83 is coupled to theother input of the second AND gate 84. The output of the second AND gate84 is coupled to the S input of one of the RS flip-flops 101-108. Theother half of the chains, 205-208, are constructed in substantially thesame manner except that the first AND gate 82 is interposed between theinput of the chain and the multiplexer 83 and the output of the Dflip-flop 81 is coupled to one of the inputs of the first AND gate 82and to one of the inputs of the multiplexer 83.

The phase splitter operates as follows: the transcoder 80 converts abinary code to a linear one, in which the number of ones produced on theoutputs of the transcoder is equal to the numeric value of the binarycode on the bus 12. The D flip-flops 81 store a previous linear code andthe first AND gates 82 subtract the previous code from its currentvalue. The resulting difference is transmitted via the multiplexers 83to the second AND gates 84, which enable f_(r) pulses to pass to the Sinputs of corresponding RS flip-flops 101 through 108. The results ofsubtraction are used in all clock periods up to the full capacity ofaccumulator 5, and hence, of the transcoder 80. Up to this moment thereis no overflow pulse on the control inputs of multiplexers 83 and eachmultiplexer passes an output signal of a respective first AND gate. Assoon as the accumulator overflows, an overflow pulse on the controlinputs of the multiplexers switches the outputs of first AND gates offthe multiplexers. Simultaneously, in the chains 201 through 204,corresponding to less-significant bits of code number X_(m), themultiplexers connect respective outputs of the transcoder, and in chains205 through 208, respective outputs of the D-flip-flops. In order tostart a next cycle of transcoder filling, it is necessary to providerotation of X_(m) ones (three ones in the above example) on outputs ofthe multiplexers, forming together a ring-like structure. Under controlof the logic level from the multiplexer output to the input of thesecond AND gate 84, an f_(r) pulse is passed, or is not passed, to theS-input of a corresponding RS flip-flop.

Suppose that n=k, i.e. all bits of the accumulator are used to drive aphase splitter. Let's take for example n=3, x=3, and w=8. According toabove-described action of the phase splitter, f_(r) pulses appear on theS inputs of the RS flip-flops as shown in Table 1. In this table, "1"denotes a presence of a pulse on the S input of a correspondingflip-flop.

                                      TABLE I                                     __________________________________________________________________________                 No of Clock                                                                   1 2 3 4 5 6 7 8 9 10                                                                              11                                                                              12                                                                              13                                                                              14                                                                              . . .                                __________________________________________________________________________    No. of flip flop, and                                                         presence of pulse on S-input                                                  1                1     1   1     1     1 . . .                                2            1   1     1     1   1     1 . . .                                3            1     1   1     1     1   1 . . .                                4            1     1     1   1     1     . . .                                5              1   1     1     1   1     . . .                                6              1     1   1     1     1   . . .                                7              1     1     1   1     1   . . .                                8                1   1     1     1   1   . . .                                __________________________________________________________________________

As can be seen from Table 1, in each clock period, the pulses appear atthe S inputs of three adjacent flip-flops, and each clock pulse shiftsthe pulses by three flip-flops, in ring-like cadence.

As mentioned above with reference to FIG. 1, the R inputs of the RSflip-flops 101-108 are coupled to the outputs of a pulse distributor 9.In the case where the pulse distributor 9 is a ring counter, in eachclock period, an f_(s) pulse appears at the R input of only oneflip-flop, and a next clock shifts it to the next flip-flop.

Turning now to FIGS. 6a through 6e, the inputs and outputs of the RSflip-flops are illustrated in a series of timing diagrams where thepulse widths are expressed in relative units and the vertical scale forthe E(t) function assumes a unity weight of one data bit to a KRresistive ladder. FIG. 6a shows the clock pulses f_(r) and f_(s). Asmentioned above, each of the output signals of the RS flip-flops summedby the KR resistive ladder has a fractional interference with a periodof q=2^(n) =8 periods of f_(r) pulses. The interference expresses itselfas duty cycle modulation of flip-flop output pulses, the pulse widthsbeing equal to 23, 18, and 13 relative units. As can be seen in FIG. 6b,the flip-flop output wave forms 1-8 are shifted in time with respect toeach other by q/k=one period. The wave forms, delayed relative to thefirst one, go in the following sequence: 1, 4, 7, 2, 5, 8, and 6. Theirsum, however, does not depend on their sequence. The sum function E(t),shown in FIG. 6c, contains a constant component E_(y), and two saw-toothperiodic components E_(r) (t) and E_(s) (t) which are shown in FIGS. 6dand 6e respectively. There is no fractional interference in thisprocess, or function. The constant component E_(y), which isproportional to an equivalent phase shift of f_(r) and f_(s) pulses, ispassed via low-pass filter 2 (FIG. 1), to the controlling input of thecontrollable oscillator 3 (FIG. 1), while the high-frequency componentsE_(r) (t) and E_(s) (t) are easily filtered out. From the foregoing,those skilled in the art will appreciate that the phase splitting of theaccumulator bits does not generate any fractional interference and thereis thus no need for circuits to suppress such interference. Moreover,the remnant fractional interference has a period, expressed in number off_(r) pulses, of M=2^(m) =2⁰ =1.

As mentioned above with reference to FIG. 1, the R inputs of the RSflip-flops 101-108 are coupled to the outputs of a pulse distributor 9.However, it is not necessary that the number of outputs of the pulsedistributor be equal to the number of flip-flops. FIG. 7 shows how apulse distributor 9 having only four outputs is coupled to pairs offlip-flops 101-102, 103-104, 105-106, and 107-108. In this embodiment,f_(s) pulses will be applied to the R inputs of the pairs of flip-flopssimultaneously. FIGS. 8a through 8e illustrate the inputs and outputs ofthe RS flip-flops when coupled to the pulse distributor according toFIG. 7 and the accumulator is 3-bit, n=k=3.

Comparing FIGS. 6b and 8b, it will be seen that each of the pulse widthsof the outputs of the even numbered flip-flops are extended by fiverelative units, i.e. half the period of the f_(s) pulses. As seen inFIGS. 8c and 8d, this change does not change the wave form or amplitudeof the fractional interference.

Based on the above comparison, it will be understood that in the case ofa pulse distributor having only two outputs (w=2), the pulse incrementsin each group of 4 flip-flops are 3/4, 1/2, 1/4 and 0 parts of the f_(s)pulse period, respectively, in each flip-flop.

The examples discussed above with reference to FIGS. 6a through 8e,concern a three bit accumulator, i.e. where n=k=3. However, as mentionedabove, the accumulator may be more, for example, a five bit accumulatorwith n=5, k=3 and m=2. Here, the two less significant bits (m=2) areused to generate a cancelling function e_(c) (t). Taking, for example,an implementation of the invention with a five bit accumulator and apulse distributor having a capacity w=4, with an input number X=13,(meaning that the input of the three more significant bit accumulatorx_(m) =3 and the input of the less significant bit accumulator gets anumber x_(L) =1) the presence of f_(r) pulses on the S inputs of theflip-flops is shown below in Table 2. As seen in Table 2, as the clockf_(r) pulses, the less significant bits accumulator (15 in FIG. 1)produces an output x_(L) (t) which cycles from 1 through 3 and overflowsto 0.

                                      TABLE 2                                     __________________________________________________________________________    Number of Clock                                                                            1 2 3 4 5 6 7 8 9 10                                                                              11                                                                              12                                                                              13                                                                              14                                                                              . . .                                x.sub.L (t)  1 2 3 0 1 2 3 0 1 2 3 0 1 2 . . .                                __________________________________________________________________________    No. of flip flop, and                                                         presence of pulse on S-input                                                  1                1   1     1   1     1   . . .                                2            1   1     1   1     1   1   . . .                                3            1     1   1   1     1   1   . . .                                4            1     1   1     1   1     1 . . .                                5              1   1     1   1     1   1 . . .                                6              1   1     1   1     1   1 . . .                                7              1     1   1     1   1     . . .                                8                1   1     1   1   1     . . .                                __________________________________________________________________________

At the overflow of less-significant bits of the accumulator, an overflowpulse goes to the more-significant bits of the accumulator, and thenumber of "ones" in a corresponding column of Table 2 increments by one,i.e. four flip-flops switch over simultaneously, instead of three andthe next f_(s) pulse goes to two adjacent flip-flops simultaneously.FIGS. 9a through 9e show the timing diagrams associated with thisembodiment of the invention. FIG. 9a shows that with every fourth pulseof the clock signal f_(r), the less significant bits accumulatoroverflows according to the function x_(L) (t). The output of each of theeight flip-flops is shown in FIG. 9b, and E_(M) (t) denotes the sum ofthe outputs of the flip-flop s according to the portion 10 of theresistive ladder shown in FIG. 4. Each output of the flip-flops has afractional interference with a period of q=2^(n) =2⁵ =32 clock periodsof f_(r) pulses. Flip-flop switch-overs are shifted in time by q/K=M=4of clock periods, with respect to each other. It will be recalled,however, that the portion 16 of the resistive ladder in FIG. 4 also addsthe output of the less significant bits accumulator and this sum isshown in FIG. 9d as the function e_(c) (t). The sum E(t) of the processE_(M) (t) and of the canceling signal e_(c) (t) may be considered as asum of the controlling signal E_(y) and of two periodic saw-toothfunctions E_(r) (t) and E_(s) (t), having frequencies f_(r) and f_(s)respectively (FIGS. 6d and 6e), which can be filtered out by thelow-pass filter.

In yet another embodiment of the invention as shown in FIG. 10, thepulse distributor 9a shown in FIG. 1 may be constructed as a secondaccumulator unit and phase splitter. According to this embodiment, thepulse distributor 9 includes a second accumulator 28, 35 having a moresignificant bits portion 28 and a less significant bits portion 35coupled by a carry network 37 and a second phase splitter 25. Theseunits are coupled to each other in a manner similar to the units 5, 15,and 8 described above with reference to FIG. 1. A second data bus 38provides input to the accumulator 28, 35. The output of the moresignificant bits portion 28 provides input for the phase splitter 25,and the clock inputs C of the units are coupled via a clock bus 14 tothe f_(s) output 4 of the controllable oscillator 3. The coupling of theoutput 36 of the less significant bits portion 35 of the accumulator 28,35 to the DAC 1 is shown in FIG. 11. Here the DAC 1 is formed as a KR &R-4R/2 resistive ladder having inputs 10, 16, and 36. In this embodimentof the invention, the numbers present on the first and second data buses6, 38 relate to the first equation given above f_(s) =(a/b)·f_(r) wherea is the number on the first data bus 6 and b is the number on thesecond data bus 38.

In still another embodiment of the invention as shown in FIG. 12, theless significant bits portions 15 and 35 of the first and secondaccumulators shown in FIGS. 1 and 10 is constructed as a primaryaccumulator 151 and an averaging unit 152 which are both clocked byreference or output signal pulses received from bus 7 or 4 correspondingto respective portions 15 or 35. The control LSB code XL is fed to the Dinput of the primary accumulator 151 from the corresponding data bus 6or 38. The respective overflow output 17 or 37 of primary accumulator151 is coupled to the respective carry network mentioned above.

The averaging unit 152 includes an averaging accumulator 153, having a Dinput which is coupled to the output of the primary accumulator 151, aregister 154, having a D input which is coupled to the output of theaveraging accumulator 153, a delay circuit 155 and a frequency divider156. The averaging accumulator 153 is clocked by the same bus 7 or 4 asthe primary accumulator 151 and the register 154 is clocked by dividedpulses supplied by the frequency divider 156 which receives input fromthe respective clock bus 7 or 4. The delay circuit 155 also receives thedivided pulses from the frequency divider 156 and provides delayedpulses to the R input of the averaging accumulator 153 to set it to azero state. The averaging unit 152 serves to average the cancellingdigital signal XL(t) from the output of the primary accumulator 151 forsome clock cycles, e.g. for P=4 clock cycles. To do this, theaccumulator 153 has m+p bits, where p=log₂ P, e.g. p=2 when P=4. Them-bit process X_(L) (t) is applied to the m less significant bits of theD input of the accumulator 153 and a sum formed on the m moresignificant bits output of the accumulator 153 is the average value forP=2^(p) clock cycles (the output of p less significant bits is notused). The average value from the accumulator 153 is written into theregister 154 and the accumulator 153 is returned to its initial zerostate to begin another averaging. This process is repeated every P clockcycles because the frequency divider 156 is set to divide the lockcycles on bus 7 or 4 by P. The delay value in the delay circuit 155 isset to allow enough time to write the output of the accumulator 153 intothe register 154 before the accumulator 153 is returned to zero state.

Referring now to FIGS. 12, 13a and 13b, the difference ΔX(t) between theinitial digital process X_(L) (t) on the bus 6 or 38 and the averagedprocess X_(L) '(t) on the bus 16 or 36 is a periodic function having aperiod of P clock cycles. An analog equivalent of this difference is aninterference which can be filtered by the low pass filter just as thepulses of the RS flip-flops switching having approximately the sameperiod q/x clock cycles.

There have been described and illustrated herein several embodiments ofa digital frequency synthesizer. While particular embodiments of theinvention have been described, it is not intended that the invention belimited thereto, as it is intended that the invention be as broad inscope as the art will allow and that the specification be read likewise.Thus, while particular implementations of the DAC have been disclosed,it will be appreciated that other implementations could be utilized.Also, while particular embodiments of the phase splitters and pulsedistributors have been shown, it will be recognized that other types ofphase splitters and pulse distributors could be used with similarresults obtained. Moreover, while particular configurations have beendisclosed in reference to the number of bits in the accumulators, itwill be appreciated that other accumulators having different capacitiescould be used as well. It will therefore be appreciated by those skilledin the art that yet other modifications could be made to the providedinvention without deviating from its spirit and scope as so claimed.

What is claimed is:
 1. A frequency synthesizer, comprising:a) a digitalto analog converter having a first plurality of digital inputs and ananalog output; b) a low pass filter having an input and an output, saidanalog output of said digital to analog converter being coupled to saidinput of said low pass filter; c) a controllable oscillator having aninput and an output, said output of said low pass filter being coupledto said input of said controllable oscillator, and the output of thecontrollable oscillator being the output of said frequency synthesizer;d) a first accumulator having a data input, a data output, and a clockinput, said data input coupled to a first data bus and said clock inputcoupled to a reference clock; e) a first phase splitter having a datainput, a plurality of outputs, and a clock input, said data input beingcoupled to said data output of said first accumulator and said clockinput being coupled to said reference clock; f) K number of RSflip-flops, each having an S input, an R input, and an output, each ofsaid K number of RS flip-flops being coupled by its S input to arespective one of said plurality of outputs of said phase splitter, andeach of said K number of RS flip-flops being coupled by its output to arespective one of said first plurality of digital inputs of said digitalto analog converter; g) a pulse distributor having a clock input saidclock input being coupled to said output of said controllableoscillators and W number of outputs each being coupled to the R input ofa respective K/W number of flip-flops, where K/W is an integer.
 2. Afrequency synthesizer according to claim 1, wherein: K=W.
 3. A frequencysynthesizer according to claim 1, wherein:said pulse distributor is aring counter.
 4. A frequency synthesizer according to claim 1,wherein:said first accumulator has a more significant bits portion and aless significant bits portion coupled to each other by a carry network,the outputs of said more significant bits portion being coupled to saidfirst phase splitter.
 5. A frequency synthesizer according to claim 4,wherein:said digital to analog converter has a second plurality ofdigital inputs, and the outputs of said less significant bits portionare coupled to said second plurality of digital inputs of said digitalto analog converter.
 6. A frequency synthesizer according to claim 1,wherein said pulse distributor comprises:a second accumulator having adata input, a data output, and a clock input, said data input coupled toa second data bus and said clock input coupled to said output of saidcontrollable oscillator; and a second phase splitter having a datainput, a plurality of outputs, and a clock input, said data input beingcoupled to said data output of said second accumulator and said clockinput being coupled to said output of said controllable oscillator, saidplurality of outputs of said phase splitter being outputs of said pulsedistributor.
 7. A frequency synthesizer according to claim 6,wherein:said second accumulator has a more significant bits portion anda less significant bits portion coupled to each other by a carrynetwork, the outputs of said more significant bits portion being coupledto said second phase splitter.
 8. A frequency synthesizer according toclaim 7, wherein:said digital to analog converter has a third pluralityof digital inputs, and the outputs of said less significant bits portionbeing coupled to said third plurality of digital inputs of said digitalto analog converter.
 9. A frequency synthesizer according to claim 1,wherein:said first plurality of digital inputs are constructed as aKR-type resistive ladder.
 10. A frequency synthesizer according to claim5, wherein:said first plurality of digital inputs are constructed as aKR-type resistive ladder, and said second plurality of digital inputsare constructed as an R-2R resistive ladder.
 11. A frequency synthesizeraccording to claim 8, wherein:said first plurality of digital inputs areconstructed as a KR-type resistive ladder, and said second and thirdplurality of digital inputs are constructed as R-4R resistive ladders.12. A frequency synthesizer according to claim 1, wherein said firstphase splitter comprises:a transcoder having K number of outputs, Kbeing an even number, a first K/2 number of outputs corresponding toless significant bits and a second K/2 outputs corresponding to moresignificant bits; K number of chains, each of said chains comprising aD-flip-flop having a D input, a C input and an output, a first AND gatehaving two inputs and an output, a multiplexer having two data inputs, acontrol input, and an output and a second AND gate having two inputs andan output, said reference clock being coupled to the C input of each Dflip-flop, and one of the inputs of each second AND gate, an overflowoutput of said data output of said first accumulator being coupled tothe control input of each multiplexer, each respective one of said firstK/2 outputs being coupled to the D input of a respective D flip-flop, aninput of a respective first AND gate and an input of a respectivemultiplexer, the output of the D flip-flop being coupled to anotherinput of the first AND gate, the output of the first AND gate beingcoupled to another input of the multiplexer, the output of themultiplexer being coupled to an input of a respective second AND gate,the output of the second AND gate being an output of said first phasesplitter, and each respective one of said second K/2 outputs beingcoupled to the D input of a respective D flip-flop and an input of arespective first AND gate, the output of the D flip-flop being coupledto another input of the first AND gate and an input of a respectivemultiplexer, the output of the first AND gate being coupled to anotherinput of the multiplexer, the output of the multiplexer being coupled toan input of a respective second AND gate, the output of the second ANDgate being an output of said first phase splitter.
 13. A frequencysynthesizer according to claim 6, wherein said second phase splittercomprises:a transcoder having K number of outputs, K being an evennumber, a first K/2 number of outputs corresponding to less significantbits and a second K/2 outputs corresponding to more significant bits; Knumber of chains, each of said chains comprising a D-flip-flop having aD input, a C input and an output, a first AND gate having two inputs andan output, a multiplexer having two data inputs, a control input, and anoutput and a second AND gate having two inputs and an output, saidoutput of said controllable oscillator being coupled to the C input ofeach D flip-flop, and one of the inputs of each second AND gate, anoverflow output of said data output of said second accumulator beingcoupled to the control input of each multiplexer, each respective one ofsaid first K/2 outputs being coupled to the D input of a respective Dflip-flop, an input of a respective first AND gate and an input of arespective multiplexer, the output of the D flip-flop being coupled toanother input of the first AND gate, the output of the first AND gatebeing coupled to another input of the multiplexer, the output of themultiplexer being coupled to an input of a respective second AND gate,the output of the second AND gate being an output of said second phasesplitter, and each respective one of said second K/2 outputs beingcoupled to the D input of a respective D flip-flop and an input of arespective first AND gate, the output of the D flip-flop being coupledto another input of the first AND gate and an input of a respectivemultiplexer, the output of the first AND gate being coupled to anotherinput of the multiplexer, the output of the multiplexer being coupled toan input of a respective second AND gate, the output of the second ANDgate being an output of said second phase splitter.
 14. A frequencysynthesizer according to claim 5, wherein said less significant bitsportion of said first accumulator comprises:i) a primary accumulatorhaving a D input, a C input, an output, and an overflow output; ii) anaveraging unit having a D input, a C input, and an output; saidreference clock being coupled to said C input of said primaryaccumulator and said C input of said averaging unit; said first data busbeing coupled to said D input of said primary accumulator; said outputof said primary accumulator being coupled to said D input of saidaveraging unit; said overflow output of said primary accumulator beingcoupled to said carry network; and said output of said averaging unitbeing coupled to said second plurality of digital inputs of said digitalto analog converter.
 15. A frequency synthesizer according to claim 14,wherein said averaging unit comprises:i) an averaging accumulator havinga capacity of p bits more than said primary accumulator, a lesssignificant bits D input coupled to said output of said primaryaccumulator, a C input coupled to said reference clock, an R input, anda more significant bits output; ii) a register having a D input coupledto said more significant bits output of said averaging accumulator, anoutput coupled to said second plurality of digital inputs of saiddigital to analog converter, and a C input; iii) a delay circuit havingan input and an output coupled to said R input of said averagingaccumulator; and iv) a frequency divider having an input coupled to saidreference clock and an output coupled to said C input of said registerand to said input of said delay circuit.
 16. A frequency synthesizeraccording to claim 8, wherein said less significant bits portion of saidsecond accumulator comprises:i) a primary accumulator having a D input,a C input, an output, and an overflow output; ii) an averaging unithaving a D input, a C input, and an output; said output of saidcontrollable oscillator being coupled to said C input of said primaryaccumulator and said C input of said averaging unit; said second databus being coupled to said D input of said primary accumulator; saidoutput of said primary accumulator being coupled to said D input of saidaveraging unit; said overflow output of said primary accumulator beingcoupled to said carry network of said second accumulator; and saidoutput of said averaging unit being coupled to said third plurality ofdigital inputs of said digital to analog converter.
 17. A frequencysynthesizer according to claim 16, wherein said averaging unitcomprises:i) an averaging accumulator having a capacity of p bits morethan said primary accumulator, a less significant bits D input coupledto said output of said primary accumulator, a C input coupled to saidoutput of said controllable oscillator, an R input, and a moresignificant bits output; ii) a register having a D input coupled to saidmore significant bits output of said averaging accumulator, an outputcoupled to said third plurality of digital inputs of said digital toanalog converter, and a C input; iii) a delay circuit having an inputand an output coupled to said R input of said averaging accumulator; andiv) a frequency divider having an input coupled to said output of saidcontrollable oscillator and an output coupled to said C input of saidregister and to said input of said delay circuit.
 18. A frequencysynthesizer according to claim 15, wherein:said frequency divider has aratio of 1:2P.
 19. A frequency synthesizer according to claim 17,wherein:said frequency divider has a ratio of 1:2P.